SPC572L64F2 datasheet(104/112 Pages) STMICROELECTRONICS

104 / 112 page

Revision history

SPC572Lx

104/112

DocID027866 Rev 5

03-Apr-2013

(cont.)

Table 25 (SARn ADC electrical specification):

Row VDD_HV_ADR_S removed.

In row V

IN Max Value cell changed to V

DD_HV_ADR (was VDD_HV_ADR_S)

In row TUE12 updated conditions

In row TUE10 changed Characteristic for both conditions to T and updated conditions

In row VALTREF changed the Parameter Classification to C (was P).

Added phrase For parameters classified as T and D. to footnote TUE and DNL...

Table 26 (SDn ADC electrical specification)

In row f

IN - changed Parameter Classification for both conditions to D (was P)

Removed rows – VDD_HV_ADV, VSS_HV_ADR_D, VDD_HV_ADR_D

For VIN_PK2PK (Input range peak to peak VIN_PK2PK =VINP –VINM) corrected GAIN

condition for Single ended – VINM =0.5*VDD_HV_ADR_D GAIN = 2,4,8,16.

δGROUP condition OSR = 75, changed Max Value to 596.

Added footnote VINM is the input voltage applied to the negative terminal of the SDADC.

For rows SNRDIFF150, SNRDIFF333 and SNRSE150 added footnote SNR degradated by

3dB, in the range 3.6 V< VDD_HV_ADV < 5.5 V.

Table 27 (Temperature sensor electrical characteristics):

In row ITEMP_SENS changed description to VDD_HV_ADV power supply current.

Section 3.15.2, Main voltage regulator electrical characteristics:

Changed HV and BV supply voltage descriptions.

Table 31 (Voltage regulator electrical characteristics):

Updated all values.

Figure 19 (Voltage monitor threshold definition):

Reworked diagram

Table 32 (Voltage monitor electrical characteristics):

Refomatted table and updated all content.

Table 34 (Functional terminals state during power-up and reset):

in TERMINAL ERROR row removed Comments.

Section 3.16, Flash memory electrical characteristics:

Added content relating to Flash read wait states and added Table 35 (RWSC settings).

Table 36 (Flash memory program and erase specifications (pending silicon

characterization)):

Updated footnotes, parameter classifications, Initial Max 25 °C values, Initial max

parameter classifications and Typical end of life values.

Added rows tpprogrameep and tqprogrameep

In Rows t16kprogrameep and t16keraseeep changed partition information to partition 1.

Table 41 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,

CPHA = 0 or 1)

Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.

Table 42 (DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,

CPHA = 0 or 1)

Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.

Table 49 (DSPI LVDS slave timing – full duplex – modified transfer format

(MTFE = 0/1)):

Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.

Table 49 (UART frequency support):

Added row clock frequency 100.

Section 4.2: eTQFP80 case drawing

Added mechanical drawings.

Section 4.3: eTQFP100 case drawing

Added mechanical drawings.

Table 53 (Thermal characteristics for eTQFP80):

Table 55. Document revision history (continued)

Date

Revision

Changes

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