ST25R3918 datasheet(127/141 Pages) STMICROELECTRONICS

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DS13490 Rev 2

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ST25R3918

Electrical characteristics

140

5.4

Electrical characteristics

Table 111. ST25R3918 electrical characteristics (VDD = 3.3 V) (1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

IPD

Supply current in Power-down mode

TJun = -40 °C to 25 °C (3)

-0.8

2.5

µA

TJun = 85 °C (3)

-2

TJun = 125 °C (3)

-12

INFCT

Supply current in Initial NFC target mode

TJun = -40 °C to 25 °C (4)

-3.5

7.0

µA

TJun = 85 °C (4)

-5

TJun = 125 °C (4)

-14

IWU

Supply current in Wake-up mode

(logic and RC oscillator)

TJun = -40 °C to 25 °C (5)

-3.0

6.3

µA

TJun = 85 °C (5)

2.8

TJun = 125 °C (5)

IRD

Supply current in Ready mode

(6)

-4.5

7.5

IAL

Supply current all active

(7)

-16

IAL-AM

Supply current all active, AM

(8)

-17

IAL1

Supply current all active single RX channel

(9)

-11

RRFO

RFO1 and RFO2 driver output resistance

IRFO = 10 mA

6.8

Ω

VRFI

RFI input sensitivity

(10) (11)

-0.5

mVrms

RRFI

RFI input resistance

kΩ

VPOR

Power on reset voltage

1.0

1.45

2.0

VAGDC

AGDC voltage

(6) (12)

1.4

1.5

1.6

VREG

Regulated voltage

(13)

2.65

3.00

3.20

1. 3.3 V supply mode with VDD = 3.3 V, unless specified otherwise. Regulated voltages are set at 3.0 V (unless specified

otherwise), 27.12 MHz Xtal connected to XTO and XTI.

2. Minimum and maximum values tested in production at 25 °C, other temperature values evaluated by characterization.

3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), other registers in default state.

4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 03h (external field detector enable),

03h to E8h (enable NFC Target mode), other registers in default state.

5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 04h (enable Wake-up mode), 32h to

08h (100 ms timeout, IRQ at every timeout), other registers in default state.

6. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to

D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D.

7. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX,

enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default state, short

VDD_A and VDD_D.

8. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX,

enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other

registers in default state, short VDD_A and VDD_D.

9. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to E8h (enable RX, 1

RX channel, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default

state, short VDD_A and VDD_D.

10. fSUB = 848 kHz, AM channel with peak detector input stage selected.

11. Specified by design, not tested in production.

12. Evaluated by characterization, not tested in production.

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