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TMS28F004ASB70CDCDL Datasheet(PDF) 38 Page - Texas Instruments |
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TMS28F004ASB70CDCDL Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 80 page  TMS28F004Axy, TMS28F400Axy 524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS829A – JANUARY 1996 – REVISED AUGUST 1997 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of supply voltage (commercial and extended temperature ranges) read operations ALT ’28F004AEy 60 ’28F400AEy 60 ’28F004AEy 70 ’28F400AEy 70 PARAMETER ALT. SYMBOL 3-V VCC RANGE 5-V VCC RANGE 3-V VCC RANGE 5-V VCC RANGE UNIT MIN MAX MIN MAX MIN MAX MIN MAX ta(A) Access time from A0 – A17 (see Note 15) tAVQV 110 60 130 70 ns ta(E) Access time from E tELQV 110 60 130 70 ns ta(G) Access time from G tGLQV 65 35 80 40 ns tc(R) Cycle time, read tAVAV 110 60 130 70 ns td(E) Delay time, E low to low-impedance output tELQX 0 0 0 0 ns td(G) Delay time, G low to low-impedance output tGLQX 0 0 0 0 ns tdis(E) Disable time, E to high-impedance output tEHQZ 55 25 70 30 ns tdis(G) Disable time, G to high-impedance output tGHQZ 45 25 55 30 ns th(D) Hold time, DQ valid from A0 – A17, E, or G, whichever occurs first (see Note 15) tAXQX 0 0 0 0 ns tsu(EB) Setup time, BYTE from E low tELFL tELFH 5 5 5 5 ns td(RP) Output delay time from RP high tPHQV 800 450 800 450 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in the high-impedance state tFLQZ 45 25 55 30 ns ta(BH) Access time from BYTE going high tFHQV 110 60 130 70 ns NOTE 15: A–1 – A17 for byte-wide |
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