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TMS28F004ASB70CDCDL Datasheet(PDF) 66 Page - Texas Instruments |
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TMS28F004ASB70CDCDL Datasheet(HTML) 66 Page - Texas Instruments |
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66 / 80 page  TMS28F004Axy, TMS28F400Axy 524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS829A – JANUARY 1996 – REVISED AUGUST 1997 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics for TMS28F400AZy over recommended ranges of supply voltage (automotive temperature range) (continued) read operations ALT ’28F004AZy 70 ’28F400AZy 70 ’28F004AZy80 ’28F400AZy80 ’28F004AZy90 ’28F400AZy90 PARAMETER ALT. SYMBOL 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE UNIT MIN MAX MIN MAX MIN MAX td(RP) Output delay time from RP high tPHQV 300 300 300 ns tdis(BL) Disable time, BYTE low to DQ8 – DQ15 in high-impedance state tFLQZ 30 30 35 ns ta(BH) Access time from BYTE going high tFHQV 70 80 90 ns timing requirements for TMS28F004AZy and TMS28F400AZy (commercial and extended temperature ranges) write/erase operations — W-controlled writes ALT ’28F004AZy 60 ’28F400AZy 60 ’28F004AZy70 ’28F400AZy70 ’28F004AZy80 ’28F400AZy80 ALT. SYMBOL 5-V VCC RANGE 5-V VCC RANGE 5-V VCC RANGE UNIT MIN MAX MIN MAX MIN MAX tc( W ) Cycle time, write tAVAV 60 70 80 ns tc( W )OP Cycle time, duration of programming operation tWHQV1 6 6 6 µs tc( W )ERB Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 0.6 s td(RPR) Delay time, boot-block relock tPHBR 100 100 100 ns th(A) Hold time, A0 – A17 (see Note 15) tWHAX 0 0 0 ns th(D) Hold time, DQ valid tWHDX 0 0 0 ns th(E) Hold time, E tWHEH 0 0 0 ns th( VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 ns tsu(A) Setup time, A0 – A17 (see Note 15) tAVWH 50 50 50 ns tsu(D) Setup time, DQ tDVWH 50 50 50 ns tsu(E) Setup time, E before write operation tELWL 0 0 0 ns tsu(RP) Setup time, RP at VHH to W going high tPHHWH 100 100 100 ns tsu( VPP)1 Setup time, VPP to W going high tVPWH 100 100 100 ns tw( W ) Pulse duration, W low tWLWH 50 50 50 ns tw( WH) Pulse duration, W high tWHWL 10 20 30 ns trec(RPHW) Recovery time, RP high to W going low tPHWL 450 450 450 ns NOTE 15: A–1 – A17 for byte-wide |
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