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TAS2780RYAR Datasheet(PDF) 64 Page - Texas Instruments

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Part # TAS2780RYAR
Description  TAS2780 Digital Input Mono Class-D Audio Amplifier With Speaker IV Sense
PDF  97 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS2780RYAR Datasheet(HTML) 64 Page - Texas Instruments

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8.9.77 INT_LTCH4 (page=0x00 address=0x51) [reset=00h]
Bit
Field
Type
Reset
Description
7-3
Reserved
R
0h
Reserved
2
IR_TDMCEIR
R
0h
TDM clock error type = Invalid SBCLK ratio or sampling rate
0b = Not detected during TDM clock error
1b = Detected during TDM clock error
1
IR_TDMCEFC
R
0h
TDM clock error type = Sampling rate changed on the fly
0b = Detected during TDM clock error
1b = Not detected during TDM clock error
0
IR_TDMCERC
R
0h
TDM clock error type = SBCLK ratio changed on the fly
0b = Not detected during TDM clock error
1b = Detected during TDM clock error
8.9.78 VBAT_MSB (page=0x00 address=0x52) [reset=00h]
Bit
Field
Type
Reset
Description
7-0
VBAT1S_CNV[11:4]
R
0h
Returns SAR ADC VBAT1S conversion MSBs.
{hex2dec(VBAT1S_CNV[11:0])}/128
8.9.79 VBAT_LSB (page=0x00 address=0x53) [reset=00h]
Bit
Field
Type
Reset
Description
7-4
VBAT1S_CNV[3:0]
R
0h
Returns SAR ADC VBAT1S conversion LSBs.
{hex2dec(VBAT1S_CNV[11:0])}/128
3-0
Reserved
R
0h
Reserved
8.9.80 PVDD_MSB (page=0x00 address=0x54) [reset=00h]
Bit
Field
Type
Reset
Description
7-0
PVDD_CNV[11:4]
R
0h
Returns SAR ADC PVDD conversion MSBs.
{hex2dec(PVDD_CNV[11:0])}/64
8.9.81 PVDD_LSB (page=0x00 address=0x55) [reset=00h]
Bit
Field
Type
Reset
Description
7-4
PVDD_CNV[3:0]
R
0h
Returns SAR ADC PVDD conversion LSBs.
{hex2dec(PVDD_CNV[11:0])}/64
3-0
Reserved
R
0h
Reserved
8.9.82 TEMP (page=0x00 address=0x56) [reset=00h]
Bit
Field
Type
Reset
Description
7-0
TMP_CNV[7:0]
R
0h
Returns SAR ADC temp sensor conversion.
{hex2dec(TMP_CNV[7:0])} - 95
8.9.83 INT_CLK_CFG (page=0x00 address=0x5C) [reset=19h]
Bit
Field
Type
Reset
Description
7
CLK_PWR_UD_EN
RW
0h
Clock based device power up/power down feature
0h = Disabled
1h = Enabled
6
DIS_CLK_HALT
RW
0h
Clock halt timer
0h = Enable clock halt detection, after clock error detected
1h = Disable clock halt detection, after clock error detected
TAS2780
SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022
www.ti.com
64
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TAS2780



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