L9374LF datasheet(57/80 Pages) STMICROELECTRONICS

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L9374LF

Programmers guide

This programmers guide is a reference section intended to aid in the L9374LF interface

software development. The L9374LF uses SPI messaging for all of its communication into

or out of the device. The Command registers are written to and the Status registers are

read.

5.1

Command registers

The Command Registers are registers written to by the MASTER

C to actuate the

L9374LFs various functions. Each command consists of an address, data, and a parity bit

(refer to Chapter 4.1: SPI serial peripheral interface for more details).

5.1.1

Sync + Sync-trigger register (address 0)

For this section see Chapter 4.3: Synchronization controller for more details

Synchronization value:

This 6-bit-value represents a time value. At this time the new set points are processed.

Resolution of LSB: 250 μs

Reset value:

With this value the time base of the synchronization can be modified.

Resolution of LSB: 1 ms

The MSB of the RESET_VALUE (D9) affects the bit times for the Sync Trigger Window, the

Duration x, and the Duration y parameters.

Sync-trigger:

The synchronization is re-triggered by setting this bit to ‘1’. After a re-synchronization the

internal logic will clear this bit automatically.

If the SVDT is active and still running, it will be interrupted by setting the SYNC_TRIG bit

(See also Chapter 4.3 section on Synchronization controller programming).

MSB

LSB

0000

SYNC_

TRIG

RESET_VALUE

SYNC_VALUE

Parity

D10

Table 40. Sync + Sync-trigger register

Sync + sync-trigger

Name

Bit Location

Number of

bits

bit time

Synchronization value

SYNC_VALUE

D0-D5

250

μs

Reset value (highest 4 Bits)

RESET_VALUE

D6-D9

1 ms

Sync-trigger

SYNC_TRIG

D10

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