L9374LF datasheet(26/80 Pages) STMICROELECTRONICS

26 / 80 page

Circuit description

L9374LF

26/80

DocID025414 Rev 1

Status buffer (data out)

A more detailed explanation about the register settings can be found in section Section 5:

Programmers guide.

4.2

Clock

The clock controller contains a CLKIN-monitoring function to validate the CLKIN frequency,

a clock multiplier to produce an internal 2 MHz clock, and an internal oscillator for

monitoring purposes and backup.

Figure 13. Clock block diagram

4.2.1

Clock multiplier

The Clock Multiplier provides a steady 2MHz signal (fCLK) for the internal logic based on the

CLKIN signal. The multiplier factor is determined by setting the CLKIN_S bits in the SPI

Command register Configuration register 1 (address 2). It is possible to have the wrong

CLKIN_S bits set for a specific CLKIN frequency. When this occurs a CLKIN failure

(CLKIN_F) is registered.

Table 29. Status buffer (data_out)

Address(HEX)

Content

Buffer name

General status

G_STATUS

Q1 output status register

STATUS_Q1

Q2 output status register

STATUS_Q2

Q3 output status register

STATUS_Q3

Q4 output status register

STATUS_Q4

Voltage of Dx

Output-duty Q3

OUT_DUTY_Q3

Output-duty Q4

OUT_DUTY_Q4

ISAT value for Q3

ISAT_Q3

ISAT value for Q4

ISAT_Q4

Internal diode Voltage measurement

V_FWD

Measurement resistor

Current controller status

CC-STATUS

Error average Q3

ERRORAVG_Q3

Error average Q4

ERRORAVG_Q4

Reserved → data ‚000 0000 0000‘

RESERVED

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