ES I

ES I

14

Rev. 0D May 11 , 2006

ES25P40

Excel Semiconductor inc.

ADVANCED INFORMATION

The protection features of the device are summa-

rized in Table 4.

When the Status Register Write Disable (SRWD) bit

of the Status Register is 0 (its initial delivery state),

it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previ-

ously been set by a Write Enable (WREN) instruc-

tion, regardless of the whether Write Protect (W#) is

driven High or Low.

When the Status Register Write Disable (SRWD) bit

of the Status Register is set to 1, two cases need to

be considered, depending on the state of Write Pro-

tect (W#).

1) If Write Protect (W#) is driven High, it is possible

to write to the Status Register provided that the

Write Enable Latch (WEL) bit has previously been

set by a Write Enable (WREN) instruction.

2) If Write Protect (W#) is driven Low, it is not possi-

ble to write to the Status Register even if the Write

Enable Latch (WEL) bit has previously been set by

a Write Enable (WREN) instruction. (Attempts to

write to the Status Register are rejected, and are

not accepted for execution).

As a consequence, all the data bytes in the memory

area that are software protected (SPM) by the

Block Protect (BP2, BP1, BP0) bits of the Status

Register, are also hardware protected against data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered :

1) by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W#) Low

2) or by driving Write Protect (W#) Low after setting

the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W#)

High.

If Write Protect (W#) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP2, BP1, BP0)

bits of the Status Register, can be used.

Table 4. Protection Modes

W# Signal

SRWD Bit

Mode

Write Protection of the Sta-

tus Register

Protected Area

(See Note)

Unprotected Area

(See Note)

11

Software

Protected

(SPM)

Status Register is Writable

(if the WREN instruction has

set the WEL bit).

The values in the SRWD,

BP2, BP1 and BP0 bits can

be changed.

Protected against

Page Program and

Erase(SE, BE,PE)

Ready to accept Page

Program and Sector

Erase Instructions

10

00

01

Hardware

Protected

(HPM)

Status Register is Hardware

write protected.

The values in the SRWD,

BP2, BP1 and BP0 bits can-

not be changed

Protected against

Page Program and

Erase (SE,BE,PE)

Ready to accept Page

Program and Sector

Erase Instructions

Note:

1. As defined by the values in the Block Protected (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.