ES25P40 datasheet(20/35 Pages) EXCELSEMI

20 / 35 page

ES I

Rev. 0D May 11 , 2006

ES25P40

Excel Semiconductor inc.

ADVANCED INFORMATION

Figure 15. Bulk Erase ( BE ) Instruction Sequence

SCK

CS#

Instruction

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets to 1(FFh) all bits

inside the entire memory. Before it can be accepted,

a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN)

instruction has been decoded, the device sets the

Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving

Chip Select (CS#) Low, followed by the instruction

code, Serial Data Input (SI). No address is required

for the Bulk Erase (BE). Chip Select (CS#) must be

driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

As soon as Chip Select (CS#) is driven High, the

self-timed Bulk Erase cycle (whose duration is tBE)

is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to check

the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is

reset.

A Bulk Erase (BE) instruction is executed only if all

the Block Protect (BP2, BP1, BP0) bits (see Table

1) are set to 0. The Bulk Erase (BE) instruction is

ignored if one or more sectors are protected.

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