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PI7C9X752 Datasheet(PDF) 8 Page - Diodes Incorporated

Part # PI7C9X752
Description  High Performance 1.62V To 3.6V Dual Uart with 64-Byte FIFO
PDF  47 Pages
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Manufacturer  DIODES [Diodes Incorporated]
Direct Link  http://www.diodes.com
Logo DIODES - Diodes Incorporated

PI7C9X752 Datasheet(HTML) 8 Page - Diodes Incorporated

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www.diodes.com
April 2019
Diodes Incorporated
PI7C9X752
Document Number DS40312 Rev 3-2
A product Line of
Diodes Incorporated
PI7C9X752
Functional Description
The PI7C9X752 integrates the functions of 4 enhanced 16C550 UARTs. Each UART channel has its own 16C550 UART compatible
configuration register set for individual channel control, status, and data transfer. Additionally, each UART channel has 64-byte
of transmit and receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and special
character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and
decoder (IrDA ver. 1.0 and 1.1), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 16Mbps
with 4X sampling clock. The PI7C9X752 is a 1.62-3.6V device with 5 volt tolerant inputs (except XTAL1).
The PI7C9X752 comes with packages: 48-pin QFP which offer both Intel and Motorola interface.
1. Trigger Levels
The PI7C9X752 provides independent selectable and programmable trigger levels for both Receiver and transmitter DMA and inter-
rupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one character. The selectable trigger levels are controlled via Register TLR (if TLR is non-zero) or (if TLR is zero) via FIFO Control
Register (FCR) and Feature Control Register(FCTR). Refer to Table 1.
Table 1. Transmit and Receive FIFO Trigger Table and Level Selection
Trigger
FCTR
BIT-5
FCTR
BIT-4
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT-4
Receive Trigger Level Transmit Trigger
Level
Table-A
0
0
0
0
1
1
0
1
0
1
0
0
1(Default)
4
8
14
1(Default)
Table-B
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
24
28
16
8
24
30
Table-C
1
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
Table-D
1
1
X
X
X
X
Programmable via RX-
TRG register
Programmable via TX-
TRG register



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