| Electronic Components Datasheet Search |
|
PI7C9X752FAEX Datasheet(PDF) 28 Page - Diodes Incorporated |
|
|
|||||||||||||||||||||||||||||
PI7C9X752FAEX Datasheet(HTML) 28 Page - Diodes Incorporated |
|
28 / 47 page ![]() 28 www.diodes.com April 2019 Diodes Incorporated PI7C9X752 Document Number DS40312 Rev 3-2 A product Line of Diodes Incorporated PI7C9X752 Offset 05H(default=60H)--- Line Status Register (LSR). Accessible when LCR[7]=0. Bit Type Description 7 RO Receiver FIFO Data Error Flag. 0 = No FIFO Error 1 = a flag for the sum of all error bits(parity error, framing error, or break)in the RX FIFO. This bit clears when there is no more error in any of the bytes in the RX FIFO 6 RO THR and TSR Empty Flag This bit is set whenever the transmitter goes idle, it clears whenever either the THR or TSR contains a data character. 5 RO THR Empty Flag This bit is set when the last data byte is transferred from THR to TSR. 5 RW When set,Xon Any function is enabled and receiving any character will resume transmit operation. The RX character will be loaded into the RX FIFO, unless the RX character is an Xon/Xoff character and receiver software flow control is enabled. 4 RW When set, internal loopback mode is enabled and TX output is looped back to the RX input internally, and MCR[1:0] signals are looped back into MSR[4:5] 3 RW Interrupt output control 0 = Forces the INT(A-D) output to high-impedance state (interrupt disable) 1 = INT(A-D) outputs to the active state (interrupt enable) The interrupt enable state can be overridden by INTSEL pin: INTSEL MCR[3] INTA-D outputs in 16 mode 0 0 Hi-Z 0 1 Active 1 X Active If Internal Loopback Mode(MCR[4]=1) is enabled, This bit is OP2 and is outputted to CD internally OP2# can be used as a general purpose output: 0 = OP2# output set HIGH 1 = OP2# output set LOW 2 RW FIFORdy register read enabled when MCR[4]=0 and ASR[0]=0 or OP1 if Internal Loopback Mode(MCR[4]=1) is enabled and is outputted to RI internally 1 RW RTS pin control: 0 = force RTS pin High 1 = force RTS pin Low When internal loopback mode, it controls MSR[4]. if Auto-RTS is enabled, the RTS pin is controlled by hardware flow control if the modem interface is not used, this output may be used as a general purpose output 0 RW DTR pin control: 0 = force DTR pin High 1 = force DTR pin Lowuart_transmitter. When internal loopback mode, it controls MSR[5]. if the modem interface is not used, this output may be used as a general purpose output Note: MCR[7:5] can only be modified if EFR[4]=1. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |