PI7C9X752FAEX datasheet(34/47 Pages) DIODES

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April 2019

Diodes Incorporated

PI7C9X752

Document Number DS40312 Rev 3-2

A product Line of

Diodes Incorporated

PI7C9X752

Offset 06H(default=00)--- RS-485 Mode Control Register (RS485). Accessible when LCR[7]=1,LCR!=0xBF and

ASR[7]=1

Bit

Type

Description

[7:6]

Reserved

Auto RS-485 Polarity Inversion

This bit changes the polarity of the Auto RS-485 Direction Control output pin (RTS#). It will only af-

fect the behavior of RTS# if RS485[4]=1

0 = RTS# output is HIGH when transmitting and LOW when receiving

1 = RTS# output is LOW when transmitting and HIGH when receiving

Auto RS-485 direction control

This bit enables the transmitter to control RTS# pin

0 = transmitter does not control RTS# pin

1 = transmitter controls RTS# pin

[3:1]

Reserved

When set, enable RS-485 9-bit mode

Offset 06H(default=00H)--- Transmission Control Register (TCR). Accessible when LCR[7]=0, MCR[6]=1.

Bit

Type

Description

[7:4]

RX FIFO Resume level.

When the RX FIFO is less than or equal to the value(decimal value of TCR[7:4] multiplied by 4),the

RTS# output will be re-asserted if Auto RTS flow is used or XON character will be transmitted if Auto

XON/XOFF flow control is used. It is recommended that this value is less than the RX Trigger Level.

If TCR[7:4] is zero, the RX FIFO Resume level is defined by FCR/FCTR register(Table A-D)

[3:0]

RX FIFO Halt level.

When the RX FIFO is greater than or equal to the value(decimal value of TCR[3:0] multiplied by

4),the RTS# output will be de-asserted if Auto RTS flow is used or XOFF character will be transmitted

if Auto XON/XOFF flow control is used. It is recommended that this value is greater than the RX Trig-

ger Level. If TCR[3:0] is zero, the RX FIFO Halt level is defined by FCR/FCTR register(Table A-D)

Offset 07H(default=00H)--- Trigger Level Register (TLR). Accessible when LCR[7]=0, MCR[6]=1.

Bit

Type

Description

[7:4]

RX FIFO Trigger level.

When the number of characters received in RX FIFO is greater than or equal to the value(decimal

value of TLR[7:4] multiplied by 4), a Receive Data Ready interrupt is generated. If TLR[7:4]=0x0, then

the RX FIFO Trigger Level is the value selected by FCR[7:6] if TLR[7:4] is zero, the RX FIFO Trigger

level is defined by FCR/FCTR register(Table A-D)

Offset 05H(default=00)--- Sample Clock Register (SNR). Accessible when LCR[7]=1,LCR!=0xBF and ASR[2]=1

Bit

Type

Description

[7:4]

SCR - Sample clock value, which is used to baud rate generate

[3:0]

CPR - N number in calculating, which is used to baud rate generate

Note: 16-SCR+CPR>1, when set SNR to control the baud rate, DLD should be keep the default value 8'h00

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