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STM32W108CB Datasheet(PDF) 109 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 109 Page - STMicroelectronics |
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109 / 278 page  STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Serial interfaces Doc ID 16252 Rev 14 109/278 SCLKout MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] SCLKout MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] SCLKout MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] SCLKout Same as above except data is sent LSB first instead of MSB first. 9.3.2 Operation Characters transmitted and received by the SPI master controller are buffered in transmit and receive FIFOs that are both 4 entries deep. When software writes a character to the SCx_DR register, the character is pushed onto the transmit FIFO. Similarly, when software reads from the SCx_DR register, the character returned is pulled from the receive FIFO. If the transmit and receive DMA channels are used, they also write to and read from the transmit and receive FIFOs. When the transmit FIFO and the serializer are both empty, writing a character to the transmit FIFO clears the IDLE bit in the SCx_SPISR register. This indicates that some characters have not yet been transmitted. If characters are written to the transmit FIFO until it is full, the TXE bit in the SCx_SPISR register is cleared. Shifting out a character to the MOSI pin sets the TXE bit in the SCx_SPISR register. When the transmit FIFO empties and the last character has been shifted out, the IDLE bit in the SCx_SPISR register is set. Table 22. SPI master mode formats SCx_SPICR Frame formats MSTR LSB FIRST CPHA CPOL 10 0 0 10 0 1 10 1 0 10 1 1 11 - - |
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