STM32W108CB datasheet(167/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

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External clock source mode 2

This mode is selected by writing ECE = 1 in the TIMx_SMCR register. The counter can

count at each rising or falling edge on the external trigger input ETR.

The EXTRIGSEL bits in the TIMx_OR register select a clock signal that drives ETR, as

shown in Table 33.

PCLK (peripheral clock). When running from the 24 MHz HSE OSC, the

PCLK frequency is 12 MHz. When the 12 MHz HSI RC oscillator is in use,

the frequency is 6 MHz.

Calibrated 1 kHz internal RC oscillator

Optional 32 kHz HSE OSC

TIMxCLK pin. If the CLKMSKEN bit in the TIMx_OR register is set, this

signal is AND'ed with the TIMxMSK pin providing a gated clock input.

Figure 29 gives an overview of the external trigger input block.

Figure 29.

External trigger input block

For example, to configure the up-counter to count each 2 rising edges on ETR, use the

following procedure:

●

As no filter is needed in this example, write ETF = 0000 in the TIMx_SMCR register.

●

Set the prescaler by writing ETPS = 01 in the TIMx_SMCR register.

●

Select rising edge detection on ETR by writing ETP = 0 in the TIMx_SMCR register.

●

Enable external clock mode 2 by writing ECE = 1 in the TIMx_SMCR register.

●

Enable the counter by writing CEN = 1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the

resynchronization circuit on the ETRP signal.

Table 33.

EXTRIGSEL clock signal selection

EXTRIGSEL bits

Clock signal selection

ETR

TIMx_SMCR

divider

/1, /2, /4, /8

ETRP

filter

downcounter

CK_INT

TIMx_SMCR

CK_INT

Encoder

mode

External clock

mode 1

External clock

mode 2

Internal clock

mode

ETRF

TRGI

TI1F

TI2F

(Internal clock)

CK_PSC

TIMx_SMCR

SMS[2:0]

ETR

ECE

ETF[3:0]

ETPS[1:0]

ETP

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