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STM32W108CB Datasheet(PDF) 168 Page - STMicroelectronics

Part # STM32W108CB
Description  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108CB Datasheet(HTML) 168 Page - STMicroelectronics

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General-purpose timers
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
168/278
Doc ID 16252 Rev 14
Figure 30.
Control circuit in external clock mode 2
10.1.4
Capture/compare channels
Each capture/compare channel is built around a capture/compare register including a
shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and
an output stage with comparator and output control.
Figure 31 gives an overview of one capture/compare channel. The input stage samples the
corresponding TIy input to generate a filtered signal (TIyF). Then an edge detector with
polarity selection generates a signal (TIyFPy) which can be used either as trigger input by
the slave mode controller or as the capture command. It is prescaled before the capture
register (ICyPS).
Figure 31.
Capture/compare channel (example: channel 1 input stage)
The output stage generates an intermediate reference signal, OCyREF, which is only used
internally. OCyREF is always active high, but it may be inverted to create the output signal,
OCy, that controls a GPIO output.
Counter clock = CK_CNT = CK_PSC
Counter register
35
36
34
ETR
CNT_EN
fMASTER
ETRP
ETRF
TI1
TIMx_CCER
CC1P
divider
/1, /2, /4, /8
IC1PSC[1:0]
TI1F_ED
filter
IC1F[3:0]
downcounter
TIMx_CCMR1
Edge
Detector
TI1F_rising
TI1F_falling
To the slave mode controller
TI1FP1
11
01
TIMx_CCMR1
CC1S[1:0]
IC1
TI2FP1
TRC
(from channel 2)
(from slave mode
controller)
10
fDTS
TIMx_CCER
IC1PS
TI1F
TI2F_rising
TI2F_falling
(from channel 2)
CCIE



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