6

Application information

6.1

Input capacitor selection

The input capacitor must be rated for the maximum input operating voltage and the maximum RMS input current.

Since the step-down converter input current is a sequence of pulses from 0 A to IOUT, the input capacitor must

absorb the equivalent RMS current, which can be up to the load current divided by two (worst case, with duty

cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation

generated by the internal ESR, thereby improving system reliability and efficiency.

The RMS input current (flowing through the input capacitor) is roughly estimated by:

ICIN,RMS≅IOUT⋅ D⋅ 1−D

(7)

Actual DC/DC conversion duty cycle, D=VOUT/VIN, is influenced by a few parameters:

DMAX= VOUT+VF

VIN,MIN−VSW,MAX

DMIN= VOUT+VF

VIN,MAX−VSW,MIN

(8)

where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal high-side

MOSFET. Considering the range DMIN to DMAX it is possible to determine the maximum ICIN,RMS flowing through

the input capacitor.

The input capacitor value must be dimensioned to safely handle the input RMS current and to limit the VIN and

VCC ramp-up slew-rate to 0.5 V/µs maximum, in order to avoid the device active ESD protection turn-on.

The amount of the input voltage ripple can be roughly overestimated by:

VIN,PP=D⋅ 1−D ⋅IOUT

CIN⋅FSW +RES,IN⋅IOUT

(9)

In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is negligible.

In addition to the input RMS current handling consideration, a ceramic capacitor with appropriate voltage rating

and with a value of 1 µF or higher should always be placed between VIN and ground and between VCC and the

IC GND pin.

This solution is necessary for noise filtering purposes.

6.2

Output capacitor selection

The output capacitor is very important in order to satisfy the output voltage ripple requirements. Using a small

inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output

voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in

the open loop gain, which helps to increase the phase margin of the system. If the zero goes to very high

frequency, a typical drawback in case of ceramic output capacitor application, a type III compensation network

must be designed.

The current, in the output capacitor, has a triangular waveform which generates a voltage ripple across it. This

ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive

component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a

voltage ripple compliant with the application requirements.

The amount of the voltage ripple can be estimated starting from the current ripple obtained by the inductor

selection. Assuming ∆IL the inductor current ripple, the output voltage ripple is roughly overestimated by the

equation below:

ΔVOUT,PP≅ΔIL⋅RES,OUT+ ΔIL

8⋅FSW⋅COUT

(10)

Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor

adopted is not a multi-layer ceramic capacitor (MLCC) with a very low ESR value. The output capacitor is also

important for loop stability: it fixes the double LC filter pole and the zero due to its ESR.

A7987

Application information

DS12928 - Rev 3

page 15/36