3

Pin settings

3.1

Pin connection

Figure 3. Pin connection (top view)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VBIAS

VIN

VIN

VCC

EN

SS

SYNCH

COMP

GND

BOOT

LX

LX

PGOOD

ILIM

FSW

FB

EXPOSED

PAD TO

SGND

3.2

Pin description

Table 1. Pin description

#

Pin

Description

1

VBIAS

The auxiliary input can be used to supply part of the analog circuitry to increase the efficiency at light load. It is

typically connected to the regulated output voltage or to an external voltage rail higher than 3 V. Connect to

GND if it is not used or bypass with a 1 µF ceramic capacitor if supplied by the output voltage or by an auxiliary

rail

2

VIN

DC input voltage

3

VIN

DC input voltage

4

VCC

Filtered DC input voltage to the internal circuitry. Bypass to GND with a 1 µF ceramic capacitor

5

EN

Active high enable pin. Connect to VCC pin if it is not used

6

SS

Soft-start programming pin. An internal current generator (5 µA typ.) charges the external capacitor to

implement the soft-start

7

SYNCH Master / slave synchronization

8

COMP

Output of the error amplifier. The designed compensation network is connected on this pin.

9

FB

Inverting input of the error amplifier

10

FSW

A pull-down resistor to GND selects the switching frequency

11

ILIM

A pull-down resistor to GND selects the peak current limitation

12 PGOOD

The PGOOD open collector output is driven low when the output voltage, sensed on the FB pin, is out of

regulation

13

LX

Switching node

14

LX

Switching node

15

BOOT

Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge required to drive the

internal n-DMOS is recovered by an internal regulator during the off-time

16

GND

Signal GND

A7987

Pin settings

DS12928 - Rev 3

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