1ST040EH2F35E2VLS1 datasheet(34/39 Pages) INTEL

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1.20. Power Management

Intel Stratix 10 TX devices use the advanced Intel 14 nm tri-gate process technology,

the all new Intel Hyperflex core architecture to enable Hyper-Folding, power gating,

and optional power reduction techniques to reduce total power consumption by as

much as 70% compared to previous generation high-performance Stratix V devices.

Intel Stratix 10 standard power devices (-V) are SmartVID devices. The core voltage

supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus

voltage regulator dedicated to that Intel Stratix 10 device. Use of a PMBus voltage

regulator for each SmartVID (-V) device is mandatory; it is not an option. A code is

programmed into each SmartVID device during manufacturing that allows the PMBus

voltage regulator to operate at the optimum core voltage to meet the device

performance specifications.

With the new Intel Hyperflex core architecture, designs can run 2X faster than

previous generation FPGAs. With 2X performance and same required throughput,

architects can cut the data path width in half to save power. This optimization is called

Hyper-Folding. Additionally, power gating reduces static power of unused resources in

the FPGA by powering them down. The Intel Quartus Prime software automatically

powers down specific unused resource blocks such as DSP and M20K blocks, at

configuration time.

Furthermore, Intel Stratix 10 TX devices feature Intel’s low power transceivers and

include a number of hard IP blocks that not only reduce logic resources but also

deliver substantial power savings compared to soft implementations. In general, hard

IP blocks consume up to 50% less power than the equivalent soft logic

implementations.

1.21. Device Configuration and Secure Device Manager (SDM)

All Intel Stratix 10 TX devices contain a Secure Device Manager (SDM), which is a

dedicated triple-redundant processor that serves as the point of entry into the device

for all JTAG and configuration commands. The SDM also bootstraps the HPS, ensuring

that the HPS can boot using the same security features as the rest of the FPGA.

1. Intel® Stratix® 10 TX Device Overview

683717 | 2022.08.18

Intel® Stratix® 10 TX Device Overview

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1ST040EH2F35E2VLS1 Datasheet(PDF) 34 Page - Intel Corporation