MIMXRT8024DFP4A datasheet(2/103 Pages) NXP

2 / 103 page

Contents

i.MX RT1060X Introduction................................ 3

1.1

Features..........................................................3

1.2

Ordering information....................................... 6

Architectural Overview....................................... 8

2.1

Block diagram................................................. 8

Modules List..................................................... 10

3.1

Special signal considerations........................17

3.2

Recommended connections for unused analog

interfaces...................................................... 19

Electrical Characteristics.................................. 19

4.1

Chip-Level conditions....................................19

4.1.1

Absolute maximum ratings............................20

4.1.2

Thermal resistance....................................... 21

4.1.3

Operating ranges.......................................... 21

4.1.4

External clock sources.................................. 23

4.1.5

Maximum supply currents............................. 24

4.1.6

Low power mode supply currents................. 24

4.1.7

USB PHY current consumption.....................25

4.2

System power and clocks............................. 26

4.2.1

Power supplies requirements and restrictions

...................................................................... 26

4.2.2

Integrated LDO voltage regulator parameters

...................................................................... 27

4.2.3

PLL’s electrical characteristics......................29

4.2.4

Arm PLL........................................................ 30

4.2.5

On-chip oscillators........................................ 30

4.3

I/O parameters.............................................. 31

4.3.1

I/O DC parameters........................................31

4.3.2

I/O AC parameters........................................ 35

4.3.3

Output buffer impedance parameters........... 36

4.4

System modules........................................... 38

4.4.1

Reset timings parameters............................. 38

4.4.2

WDOG reset timing parameters....................38

4.4.3

SCAN JTAG Controller (SJC) timing

parameters....................................................39

4.4.4

Debug trace timing specifications................. 41

4.5

External memory interface............................ 42

4.5.1

SEMC specifications..................................... 42

4.5.2

FlexSPI parameters...................................... 45

4.6

Display and graphics.....................................51

4.6.1

CMOS Sensor Interface (CSI) timing

parameters....................................................51

4.6.2

LCD Controller (LCDIF) timing parameters...53

4.7

Audio.............................................................54

4.7.1

SAI/I2S switching specifications................... 54

4.7.2

SPDIF timing parameters..............................56

4.8

Analog...........................................................57

4.8.1

DCDC............................................................57

4.8.2

A/D converter................................................ 58

4.8.3

ACMP ...........................................................64

4.9

Communication interfaces............................ 65

4.9.1

LPSPI timing parameters.............................. 66

4.9.2

LPI2C module timing parameters................. 68

4.9.3

Ultra High Speed SD/SDIO/MMC Host Interface

(uSDHC) AC timing.......................................69

4.9.4

Ethernet controller (ENET) AC electrical

specifications................................................ 73

4.9.5

Flexible Controller Area Network (FLEXCAN)

AC electrical specifications........................... 76

4.9.6

LPUART electrical specifications.................. 76

4.9.7

USB PHY parameters................................... 76

4.10

Timers........................................................... 77

4.10.1

Pulse Width Modulator (PWM) characteristics

...................................................................... 77

4.10.2

Quad timer timing..........................................77

Boot mode configuration.................................. 78

5.1

Boot mode configuration pins....................... 78

5.2

Boot device interface allocation.................... 79

Package information and contact assignments

......................................................................... 84

6.1

13 x 13 mm package information..................84

6.1.1

13 x 13 mm, 0.8 mm pitch, ball matrix.......... 84

6.1.2

13 x 13 mm supplies contact assignments and

functional contact assignments.....................86

6.1.3

13 x 13 mm, 0.8 mm pitch, ball map............. 96

Legal information...............................................................99

MIMXRT8024DFP4A Datasheet(PDF) 2 Page - NXP Semiconductors

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