MIMXRT8024DFP4A datasheet(13/103 Pages) NXP

13 / 103 page

Table 2. i.MX RT1060X modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

GPT1

GPT2

General Purpose Timer

Timer Peripherals Each GPT is a 32-bit "free-running" or "set and forget"

mode timer with programmable prescaler and compare

and capture register. A timer counter value can be

captured using an external event and can be configured

to trigger a capture event on either the leading or trailing

edges of an input pulse. When the timer is configured

to operate in "set and forget" mode, it is capable of

providing precise interrupts at regular intervals with

minimal processor intervention. The counter has output

compare logic to provide the status and interrupt at

comparison. This timer can be configured to run either on

an external clock or on an internal clock.

KPP

Keypad Port

Human

Machine Interfaces

The KPP is a 16-bit peripheral that can be used as

a keypad matrix interface or as general purpose input/

output (I/O). It supports 8 x 8 external key pad matrix.

Main features are:

• Multiple-key detection

• Long key-press detection

• Standby key-press detection

• Supports a 2-point and 3-point contact key matrix

LCDIF

LCD interface

Multimedia

Peripherals

The LCDIF is a general purpose display controller used

to drive a wide range of display devices varying in size

and capabilities. The LCDIF is designed to support dumb

(synchronous 24-bit Parallel RGB interface) and smart

(asynchronous parallel MPU interface) LCD devices.

LPI2C1

LPI2C2

LPI2C3

LPI2C4

Low Power Inter

integrated Circuit

Connectivity and

Communications

The LPI2C is a low power Inter-Integrated Circuit (I2C)

module that supports an efficient interface to an I2C bus

as a master.

The I2C provides a method of communication between

a number of external devices. For detailed information,

see LPI2C module timing parameters.

LPSPI1

LPSPI2

LPSPI3

LPSPI4

Low Power Serial

Peripheral Interface

Connectivity and

Communications

The LPSPI is a low power Serial Peripheral Interface

(SPI) module that support an efficient interface to an SPI

bus as a master and/or a slave.

• It can continue operating while the chip is in stop

modes, if an appropriate clock is available

• Designed for low CPU overhead, with DMA off

loading of FIFO register access

LPUART1

LPUART2

UART Interface

Connectivity

Peripherals

Each of the UART modules support the following serial

data transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

Table continues on the next page...

NXP Semiconductors

Modules List

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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