MIMXRT8024DFP4A datasheet(49/103 Pages) NXP

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TSCKD

TSCKDQS

SIO[0:7]

DQS

SCK

Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Table 44. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-1

TSCKD

TSCK2DQS

SCK2

SIO[0:7]

DQS

SCK

Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

4.5.2.2 FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals and data outputs.

4.5.2.2.1 SDR mode

Table 45. FlexSPI output timing in SDR mode

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

1661

MHz

Tck

SCK clock period

6.0

—

TDVO

Output data valid time

—

Table continues on the next page...

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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