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SL11R

Document #: 38-08006 Rev. **

Page 39 of 85

5.1.1

I/O Control Register 0 (0xC022: R/W)

This register controls the input/output direction of the GPIO data pins from GPIO15 to GPIO0. When any bit of this register set

to one, the corresponding GPIO data pin becomes an output pin. When any bit of this register is set to zero, the corresponding

GPIO data pin becomes an input pin.

D15-0

E15-0

Enable individual outputs, GPIO 15-0. Logic ’1’ enables.

5.1.2

I/O Control Register 1 (0xC028: R/W)

This register controls the input/output direction of the GPIO data pins from GPIO31 to GPIO16. When any bit of this register set

to one, the corresponding GPIO data pin becomes an output pin. When any bit of this register is set to zero, the corresponding

GPIO data pin becomes an input pin.

D15-0

E31-16

Enable individual outputs, GPIO 31-16. Logic ’1’ enables.

5.1.3

Output Data Register 0 (0xC01E: R/W)

This register controls the output data of the GPIO data pins from GPIO15 to GPIO0.

Note: A read of this register reads back the last data written, not the data on pins configured as input (see below).

D15-0

O15-0

Output Pin Data

5.1.4

Output Data Register 1 (0xC024: R/W)

This register controls the output data of the GPIO data pins from GPIO31 to GPIO16.

D15-0

O31-16

Output Pin Data

5.1.5

Input Data Register 0 (0xC020: Read only)

This register reads the input data of the GPIO data pins from GPIO15 to GPIO0.

D15-0

I15-0

Input Pin data

5.1.6

Input Data Register 1 (0xC026: Read only)

This register reads the input data of the GPIO data pins from GPIO31 to GPIO16.

D15

D14

D13

D12

D11

D10

E15

E14

E13

E12

E11

E10

D15

D14

D13

D12

D11

D10

E31

E30

E29

E28

E27

E26

E25

E24

E23

E22

E21

E20

E19

E18

E17

E16

D15

D14

D13

D12

D11

D10

O15

O14

O13

O12

O11

O10

D15

D14

D13

D12

D11

D10

O31

O30

O29

O28

O27

O26

D15

D14

D13

D12

D11

D10

I15

I14

I13

I12

I11

I10

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