SL11R
Document #: 38-08006 Rev. **
Page 21 of 85
4.9.11
USB Endpoint 3 Count Register (0x012E: R/W)
See USB Endpoint 0 Count Register (0x0122: R/W)
4.10
Processor Control Registers
The SL11R provides software control registers that can be used to configure the chip mode, clock control, read software version
and software breakpoint control.
4.10.1
Configuration Register (0xC006: R/W)
The Configuration Register is used to configure the SL11R into the appropriate mode, and to select a clock multiplier.
Note: D6-4 and C2-0 are Clock Configuration bits. These bits select the clock source. The clock may come from an outside pin
(X1 or X_PCLK) or it may come from the PLL multiplier as indicated in the table.
D3
CD
If Clock Disable bit = ‘1’, this Clock Configuration register can no longer be modified through software writes. It is a “sticky
bit” used to lock the configuration through a write to this bit in the boot prom code.
Note:
• On the SL11R chip set, this bit will be set to zero.
• `There are four modes defined in this documentation: DVC 8-bit DMA mode, Fast EPP mode, 8/16-bit DMA mode and General
Purpose IO (GPIO) mode. All modes are pin-compatible.
D2, D1
M1,M0:
SL11R modes are selected as shown here:
D0
MD
If Mode Disable bit = ‘1’, this Configuration register can no longer be modified through software writes. It is a “sticky bit”
used to lock the configuration through a Write to this bit in the boot prom code.
Note:
By default, this bit will be set to zero by the SL11R BIOS.
D15-D7
Reserved
should be set to all zeros.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
000000000
C2
C1
C0
CD
M1
M0
MD
C2
C1
C0
PCLK
RCLK
OE
0
0
0
X1
X1
0
0
0
1
2/3*X1
X1
0
0
1
0
X_PCLK
X1
0
0
1
1
2/3*X1
X1
1
1
0
0
4*X1
4*X1
0
1
0
1
8/3*X1
4*X1
0
1
1
0
4*X1
4*X1
1
1
1
1
8/3*X1
4*X1
1
M1
M0
Mode
00
GPIO
0
1
DVC 8-Bit DMA
1
0
Fast EPP
11
8/16-Bit DMA
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