SL11R
Document #: 38-08006 Rev. **
Page 13 of 85
3.18
DMA Interface
This interface uses the same hardware as the Mailbox Interface, except that the DMA engine inside the SL11R generates DMA
requests to control the transfer. Because the DMA engine handles the transfer of data through the Input and Output buffer, there
is no need for the external system to poll the status register. The external system simply waits for a DREQ (GPIO 20) from the
SL11R and transfers data. The SL11R DMA engine can transfer data in only one direction at a time. Please note that only 16-bit
DMA transfers are supported on the SL11R.
The 22-bit DMA counter is loaded through registers 0xC02C and 0xC02E. This makes up the DMA start address and the location
of the first word to be written or read. The 22-bit DMA end address register is loaded through registers 0xC030 and 0xC032. This
will be location of the last word written into the SL11R. When reading data out of the SL11R, the end address register should be
loaded with the last address to be read from plus two. After these registers are loaded, the DMA control register (0xC0C0) must
be loaded with a 0x0007 to enable the DREQ output pin. Lastly, the other DMA control register (0xC02A) is loaded with either a
0x0001, to start DMA transfers into the SL11R, or 0x0003, to start DMA transfers out of the SL11R.
Figure 3-3. Mailbox/DMA Read
Parameter
Description
Min.
Typical
Max.
Unit
tCDQ
PCLK to DREQ high
1
17
ns
tAPW
ADDR pulse width
30
ns
tCPW
nCS pulse width
30
ns
tRPW
Read pulse width
30
ns
tRAH
ADDR hold after read high
0
ns
tRCH
nCS hold after read high
0
ns
tACC
Read access time
25
ns
tDCS
DREQ high to CS low
5
ns
tDR
DREQ high to read low
5
ns
tRHDQ
Read high to DREQ low hold
30
ns
tRDH
Read high to data hold
10
ns
nRD/GPIO16
SD15-0
DREQ/GPIO20
nCS/GPIO18
ADDR/GPIO19
PCLK
t
CDQ
t
DCS
t
CPW
t
RPW
t
ACC
t
RDH
DATA VALID
t
RHDQ
t
APW
t
DR
t
RCH
t
RAH
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