SL11R
Document #: 38-08006 Rev. **
Page 49 of 85
6.0
Physical Connection
6.1
Package Type
100 PQFP.
6.2
GPIO and 8/16-Bit DMA Modes—Pin Assignment and Description
PWM Channel 1 Start Register
0xC0EE
R/W
PWM Channel 1 Stop Register
0xC0F0
R/W
PWM Channel 2 Start Register
0xC0F2
R/W
PWM Channel 2 Stop Register
0xC0F4
R/W
PWM Channel 3 Start Register
0xC0F6
R/W
PWM Channel 3 Stop Register
0xC0F8
R/W
PWM Cycle Count Register
0xC0FA
R/W
GPIO and 8/16-Bit DMA Modes—Pin Assignment and Description
Pin Name
Pin No. GPIO Pins Pin Type
GPIO & 8/16-bit DMA modes Pin Chip Revision 1.1
VDD
1
Power
+3.3 VDC Supply
D0
2
Bidir
External Memory Data Bus, Data0
D1
3
Bidir
External Memory Data Bus, Data1
D2
4
Bidir
External Memory Data Bus, Data2
D3
5
Bidir
External Memory Data Bus, Data3
D4
6
Bidir
External Memory Data Bus, Data4
D5
7
Bidir
External Memory Data Bus, Data5
D6
8
Bidir
External Memory Data Bus, Data6
D7
9
Bidir
External Memory Data Bus, Data7
D8
10
Bidir
External Memory Data Bus, Data8
D9
11
Bidir
External Memory Data Bus, Data9
D10
12
Bidir
External Memory Data Bus, Data10
D11
13
Bidir
External Memory Data Bus, Data11
GND
14
GND
Digital ground.
X1
15
Input
External 48-MHz Crystal or Clock Input.
X2
16
Output
External crystal output. No connection when X1 is used for clock input
VDD
17
Power
+3.3 VDC Supply
D12
18
Bidir
External Memory Data Bus, Data12
D13
19
Bidir
External Memory Data Bus, Data13
D14
20
Bidir
External Memory Data Bus, Data14
D15
21
Bidir
External Memory Data Bus, Data15
A20
22
Output
External Memory Address Bus, A20
A19
23
Output
External Memory Address Bus, A19
A18
24
Output
External Memory Address Bus, A18
I/O Address Map (continued)
Function
Address
Mode
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