MCP33151-05-ESLASHMS datasheet(38/55 Pages) MICROCHIP

38 / 55 page

MCP33151/41-XX

DS20006220A-page 38

 2019 Microchip Technology Inc.

FIGURE 6-4:

Interface Timing Diagram for Accumulator Operation in 3-Wire CS Mode, Without

BUSY Status Indicator Output Bit.

6.1.1.2

3-Wire CS Mode with BUSY Output

Bit

This interface option is typically used when a single

MCP33151/41-XX is connected to an SPI-compatible

digital host that has an interrupt (IRQ) input.

Figure 6-5 shows the connection diagram with the

host device. In this mode, CNV functions as both con-

version control and CS.

To enable this interface option, SDI can either be tied

to GND, or permanently held in a Logic = 0 state. By

doing so, the device will always output a BUSY status

bit.

As shown in Figure 6-6, at the rising edge of CNV,

conversion is initiated. The SDO pin becomes High-Z

state (if no external pull-up is used). Once the conver-

sion is initiated, it continues and completes the conver-

sion regardless of the CNV pin condition. This means

the CNV pin can be used for other SPI devices after

the conversion is initiated.

When conversion is complete, the device enters an

acquisition phase and Power-Down state, SDO comes

out of the High-Z state, and outputs a BUSY status

indicator bit (Low level). The device exits the acquisi-

tion phase when CNV once again returns to a High

state. SDO then returns to a High-Z state after the 15th

SCLK falling edge or when CNV goes High, whichever

occurs first.

This configuration provides a high-to-low transition on

the IRQ pin of the digital host by the BUSY bit. The

data bits are clocked out, MSB first, on the subsequent

SCLK falling edges. Data are valid on both edges of

SCLK and can be captured on either edge. However, a

digital host capturing data on the SCLK falling edge

can achieve a faster reading rate.

Figure 6-6 and Figure 6-7 show the timing diagrams

for both early and late CNV lowering scenarios.

SDI = 1

SCLK

SDO

CNV (CS)

TCYC(1)

= 1/fs

DM-1

DM-2

DM-3

tSCLK

tDO

tSCLK_H

tSCLK_L

M-2

tCNVH

tEN

tQUIET

tDIS

ADC

State

tCNV

tSU_SDIH_CNV

tACQ

tCNVH

TCYC(N) = 1/fs

DM-4

D14

TCYC(2)

= 1/fs

tCNVH

tCNV

D15

TCYC(3) … TCYC(N-1)

tACQ

tCNV

M-1

Legend

No signal transitions during compressed time

Signal transitions during compressed time

Note:

See Section 5.7, Data Accumulator for

more details about using the data

accumulator feature.

Note:

It is recommended that CNV be driven

Low before the minimum conversion time

(tCNV) expires, and remain Low until the

maximum

possible

conversion

time

(tCONV) expires. A Low level on the CNV

input at the end of a conversion ensures

the device generates a BUSY status

indicator bit when the ADC has finished

converting.

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