MCP33151-05-ESLASHMS datasheet(7/55 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006220A-page 7

MCP33151/41-XX

Digital Inputs/Outputs

High-Level Input Voltage

VIH

0.7 x DVIO

—DVIO +0.3

DVIO ≥ 2.3V

0.9 x DVIO

—DVIO +0.3

DVIO <2.3V

Low-Level Input Voltage

VIL

-0.3

—

0.3 x DVIO

VDVIO ≥ 2.3V

-0.3

—

0.2 x DVIO

VDVIO <2.3V

Hysteresis of Schmitt

Trigger Inputs

VHYST

—0.2 x DVIO

—

All digital inputs

Low-Level Output Voltage

VOL

——

0.2 x DVIO

VIOL = 500 µA (source)

High-Level Output

Voltage

VOH

0.8 x DVIO

—

IOH =- 500 µA (sink)

Input Leakage Current

ILI

—

±1

µA

CNVST/SDI/SCLK = GND or

DVIO

Output Leakage Current

ILO

—

±1

µA

Output is high-Z, SDO = GND

or DVIO

Internal Capacitance (all

digital inputs and outputs)

CINT

—7

—

TA =+25°C (Note 1)

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD =1.8V,

DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, CLOAD_SDO =20 pF, +25°C is

applied for typical values.

MCP331X1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP331X1-05: Sample Rate (fS) = 500 ksps, SPI Clock Input (SCLK) = 30 MHz.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: Decoupling capacitor is recommended on the following pins:

(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.

4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.

5: ENOB = (SINAD – 1.76)/6.02

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