UPSD3422_V01 datasheet(164/300 Pages) STMICROELECTRONICS

164 / 300 page

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USB interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

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USB IN FIFO interrupt enable register (UIE1)

When an endpoint’s IN FIFO has been successfully sent to the host with an IN

transaction, the FIFO becomes empty. The UIE1 register is used to enable each

endpoint’s IN FIFO interrupt (Table 106).

●

USB OUT FIFO interrupt enable register (UIE1)

When an endpoint’s OUT FIFO has been filled by an OUT transaction from the host,

the FIFO becomes full. The UIE2 register is used to enable each endpoint’s OUT FIFO

interrupt (Table 108).

Table 105.

UIE0 register bit definition

Bit

Symbol

R/W

Definition

–

Reserved

–

Reserved

–

Reserved

–

Reserved

RSTIE

R/W

Enable the USB Reset interrupt

SUSPEND

R/W

Enable the USB Suspend interrupt

EOPIE

R/W

Enable the USB EOP interrupt

RESUMIE

R/W

Enable the USB Resume interrupt

Table 106.

USB IN FIFO interrupt enable register (UIE1 0E5h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

IN4IE

IN3IE

IN2IE

IN1IE

IN0IE

Table 107.

UIE1 register bit definition

Bit

Symbol

R/W

Definition

–

Reserved

–

Reserved

–

Reserved

IN4IE

R/W

Enable Endpoint 4 IN FIFO interrupt

IN3IE

R/W

Enable Endpoint 3 IN FIFO interrupt

IN2IE

R/W

Enable Endpoint 2 IN FIFO interrupt

IN1IE

R/W

Enable Endpoint 1 IN FIFO interrupt

IN0IE

R/W

Enable Endpoint 0 IN FIFO interrupt

Table 108.

USB OUT FIFO interrupt enable register (UIE2 0E6h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

OUT4IE

OUT3IE

OUT2IE

OUT1IE

OUT0IE

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UPSD3422 Datasheet(PDF) 164 Page - STMicroelectronics

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