UPSD3422_V01 datasheet(171/300 Pages) STMICROELECTRONICS

171 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422, UPSD3433, UPSD3434, UPSD3454

USB interface

171/300

●

USB endpoint0 status (USTA)

The USB Endpoint0 Status register (see Table 122) provides the status for events that

occur on the USB that are directed to endpoint0.

Caution:

Disabling and enabling the USB SIE using the USBEN bit in the UCTL register clears the

RCVT, IN, and OUT bits in this register.

Table 122.

USB endpoint0 status (USTA 0EDh, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

RCVT

SETUP

OUT

Table 123.

USTA register bit definition

Bit

Symbol

R/W

Definition

–

Reserved

–

Reserved

–

Reserved

–

Reserved

3RCVT

Received Data Toggle Bit

This bit indicates the toggle bit of the received data packet:

0 = Data0, and

1 = Data1

2SETUP

R/W

SETUP Token Detect Bit

This bit is set when Endpoint0 receives a SETUP token. This

bit is not cleared when Endpoint0 receives an IN or OUT token

following the SETUP token that set this bit. This bit is cleared

by software or a reset.

1IN

IN Token Detect Bit

This bit is set when Endpoint0 receives an IN token. This bit is

cleared when Endpoint0 receives a SETUP or OUT token.

0OUT

OUT Token Detect Bit

This bit is set when Endpoint0 receives an OUT token. This bit

is cleared when Endpoint0 receives a SETUP or IN token.

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422 Datasheet(PDF) 171 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 171 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL