UPSD3422EB40U6 datasheet(228/300 Pages) STMICROELECTRONICS

228 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

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28.5.32

Loading and reading OMCs

Each of the two OMC groups (eight OMCs each) occupies a byte in csiop space, named

MCELLAB and MCELLBC (see Table 169 and Table 170). When the 8032 writes or reads

these two OMC registers in csiop it is accessing each of the OMCs through its 8-bit data

bus, with the bit assignment shown in Table 168 on page 227. Sometimes it is important to

know the bit assignment when the user builds GPLD logic that is accessed by the 8032. For

example, the user may create a 4-bit counter that must be loaded and read by the 8032, so

the user must know which nibble in the corresponding csiop OMC register the firmware must

access. The fitter report generated by PSDsoft Express will indicate how it assigned the

OMCs and data bus bits to the logic. The user can optionally force PSDsoft Express to

assign logic to specific OMCs and data bus bits if desired by using the ‘PROPERTY’

statement in PSDsoft Express. Please see the PSDsoft Express User’s Manual for more

information on OMC assignments.

Loading the OMC flip-flops with data from the 8032 takes priority over the PLD logic

functions. As such, the preset, clear, and clock inputs to the flip-flop can be asynchronously

overridden when the 8032 writes to the csiop registers to load the individual OMCs.

MCELLBC3

Port B3 or C3

MCELLBC4

Port B4 or C4

MCELLBC5

Port B5

MCELLBC6

Port B6

MCELLBC7

Port B7 orC7

MCELLAB0-MCELLAB7 can be output to Port A pins only on 80-pin devices. Port A is not available on 52-

pin devices.

Port pins PC0, PC1, PC5, and PC6 are dedicated JTAG pins and are not available as outputs for

MCELLBC 0, 1, 5, or 6.

Table 168.

OMC port and data bit assignments (continued)

OMC

Port

assignment(1),(2)

Native product

terms from AND-OR

array

Maximum

borrowed product

terms

Data bit on 8032

data bus for

loading or

reading OMC

Table 169.

Output macrocell MCELLAB (address = csiop + offset 20h)(1)

All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on

reset).

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCELLAB

Table 170.

Output macrocell MCELLBC (address = csiop + offset 21h)(1)

All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on

reset).

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCELLBC

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UPSD3422EB40U6 Datasheet(PDF) 228 Page - STMicroelectronics

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