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UPSD3422EB40U6 Datasheet(PDF) 230 Page - STMicroelectronics |
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UPSD3422EB40U6 Datasheet(HTML) 230 Page - STMicroelectronics |
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230 / 300 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD3422, UPSD3433, UPSD3434, UPSD3454 230/300 signal to latch the incoming signal. Then define an equation for the IMC clock (.ld) or the IMC gate (.le) signal in the “I/O Equations” section. If the user would like to latch an incoming signal using the gate signal ALE from the 8032, then in PSDsoft Express, for a given input pin on Port A, B, or C, specify “Latched Address” as the pin function. If it is desired to pass an incoming signal through an IMC directly to the AND-OR array inputs without clocking or gating (this is most common), in PSDsoft Express simply specify “Logic or Address” for the input pin function on Port A, B, or C. Figure 78. Detail of a single IMC Table 173. Input macrocell port A(1) (address = csiop + offset 0Ah)(2) 1. Port A not available on 52-pin UPSD34xx devices. 2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PA7 IMC PA6 IMC PA5 IMC PA4 IMC PA3 IMC PA2 IMC PA1 IMC PA0 Table 174. Input macrocell port B (address = csiop + offset 0Bh)(1) 1. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PB7 IMC PB6 IMC PB5 IMC PB4 IMC PB3 IMC PB2 IMC PB1 IMC PB0 Table 175. Input macrocell port C (address = csiop + offset 18h)(1) (2) 1. X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins. 2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PC7 X X IMC PC4 IMC PC3 IMC PC2 X X Input macrocell (IMC) D Q G D Q M U X M U X PSDsoft 8032 data bit 8032 read of particular CSIOP IMC register PT clock or gate (.LD OR .LE) Pin input Latched input Gated input (.LD) (.LE) ALE PSDsoft ALE From I/O port logic Input signal from pin on port A, B, or C From AND-OR array To PLD input bus This signal is ganged to 3 other IMCs, grouping IMC 0 - 3 or IMC 4 - 7. AI06603b Obsolete Product(s) - Obsolete Product(s) |
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