UPSD3422EB40U6 datasheet(234/300 Pages) STMICROELECTRONICS

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

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pins, and change the output state of I/O pins by accessing the Data In, Direction, and Data

Out csiop registers respectively at run-time.

To implement MCU I/O mode, each desired pin is specified in PSDsoft Express as MCU I/O

function and given a pin name. Then 8032 firmware is written to set the Direction bit for each

corresponding pin during initialization routines (0 = In, 1 = Out of the chip), then the 8032

firmware simply reads the corresponding Data In register to determine the state of an I/O

pin, or writes to a Data Out register to set the state of a pin. The Direction of each pin may

be changed dynamically by the 8032 if desired. A mixture of input and output pins within a

single port is allowed. Figure 79 on page 232 shows the Data In, Data Out, and Direction

signal paths.

The Data In registers are defined in Table 178 to Table 181. The Data Out registers are

defined in Table 182 to Table 185 on page 235. The Direction registers are defined in

Table 186 to Table 189 on page 236.

Table 178.

MCU I/O mode port A data in register(1) (address = csiop + offset 00h) (2)

Port A not available on 52-pin UPSD34xx devices.

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Table 179.

MCU I/O mode port B data in register (address = csiop + offset 01h)(1)

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Table 180.

MCU I/O mode port C data in register (address = csiop + offset 10h)(1) (2)

X = Not guaranteed value, can be read either '1' or '0.'

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7

PC4

PC3

PC2

Table 181.

MCU I/O mode port D Data in register (address = csiop + offset 11h)(1) (2)

X = Not guaranteed value, can be read either '1' or '0.'

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD2(3)

Not available on 52-pin UPSD34xx devices.

PD1

Table 182.

MCU I/O mode port A data out register(1) (address = csiop + offset

04h)(2)(3)

Port A not available on 52-pin UPSD34xx devices.

For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’.

Default state of register is 00h after reset or power-up.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

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UPSD3422EB40U6 Datasheet(PDF) 234 Page - STMicroelectronics

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