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UPSD3422EB40U6 Datasheet(PDF) 258 Page - STMicroelectronics |
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UPSD3422EB40U6 Datasheet(HTML) 258 Page - STMicroelectronics |
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258 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD3422, UPSD3433, UPSD3434, UPSD3454 258/300 PSD module is in BYPASS mode while debugging the MCU module, and the MCU module is in BYPASS mode while performing ISP on the PSD module. The RESET_IN input pin on the UPSD34xx package goes to the MCU module, and this module will generate the RST reset signal for the PSD module. These reset signals are totally independent of the JTAG TAP controllers, meaning that the JTAG channel is operational when the modules are held in reset. It is required to assert RESET_IN during ISP. STMicroelectronics and 3rd party JTAG ISP tools will automatically assert a reset signal during ISP. However, the user must connect this reset signal to RESET_IN as shown in examples in Figure 91 on page 259 and Figure 92 on page 261. Figure 90. JTAG chain in UPSD34xx package 28.6.3 In-system programming The ISP function can use two different configurations of the JTAG interface: ● 4-pin JTAG: TDI, TDO, TCK, TMS ● 6-pin JTAG: Signals above plus TSTAT, TERR At power-up, the four basic JTAG signals are all inputs, waiting for a command to appear on the JTAG bus from programming or test equipment. When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional. The same command that enables the JTAG channel may optionally enable the two additional signals, TSTAT and TERR. JTAG TDI JTAG TMS JTAG TCK JTAG TDO TDI TMS TCK TDO TDO TMS TCK TDI PC3 / TSTAT PC4 / TERR TSTAT TERR OPTIONAL JTAG TAP CONTROLLER JTAG TAP CONTROLLER RESET_IN OPTIONAL DEBUG RESET RST 8032 MCU MCU MODULE PSD MODULE MAIN FLASH MEMORY 2ND FLASH MEMORY PLD uPSD34xx IEEE 1149.1 AI10460 Obsolete Product(s) - Obsolete Product(s) |
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