UPSD3422EB40U6 datasheet(257/300 Pages) STMICROELECTRONICS

257 / 300 page

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28.6.1

JTAG ISP and JTAG debug

An IEEE 1149.1 serial JTAG interface is used on UPSD34xx devices for ISP (in-system

programming) of the PSD module, and also for debugging firmware on the MCU module.

IEEE 1149.1 Boundary Scan operations are not supported in the UPSD34xx.

The main advantage of JTAG ISP is that a blank UPSD34xx device may be soldered to a

circuit board and programmed with no involvement of the 8032, meaning that no 8032

firmware needs to be present for ISP. This is good for manufacturing, for field updates, and

for easy code development in the lab. JTAG-based programmers and debuggers for

UPSD34xx are available from STMicroelectronics and 3rd party vendors.

ISP is different than IAP (in-application programming). IAP involves the 8032 to program

Flash memory over any interface supported by the 8032 (e.g., UART, SPI, I2C), which is

good for remote updates over a communication channel. UPSD34xx devices support both

ISP and IAP. The entire PSD module (Flash memory and PLD) may be programmed with

JTAG ISP, but only the Flash memories may be programmed using IAP.

28.6.2

JTAG chaining inside the package

JTAG protocol allows serial “chaining” of more than one device in a JTAG chain. The

UPSD34xx is assembled with a stacked die process combining the PSD module (one die)

and the MCU module (the other die). These two die are chained together within the

UPSD34xx package. The standard JTAG interface has four basic signals:

●

TDI - Serial data into device

●

TDO - Serial data out of device

●

TCK - Common clock

●

TMS - Mode Selection

Every device that supports IEEE 1149.1 JTAG communication contains a test access port

(TAP) controller, which is a small state machine to manage JTAG protocol and serial

streams of commands and data. Both the PSD module and the MCU module each contain a

TAP controller.

Figure 90 illustrates how these die are chained within a package. JTAG programming/test

equipment will connect externally to the four IEEE 1149.1 JTAG pins on Port C. The TDI pin

on the UPSD34xx package goes directly to the PSD module first, then exits the PSD module

through TDO. TDO of the PSD module is connected to TDI of the MCU module. The serial

path is completed when TDO of the MCU module exits the UPSD34xx package through the

TDO pin on Port C. The JTAG signals TCK and TMS are common to both modules as

specified in IEEE 1149.1. When JTAG devices are chained, typically one devices is in

BYPASS mode while another device is executing a JTAG operation. For the UPSD34xx, the

VM register(1)

Initialized with value that

was specified in PSDsoft

Initialized with value that

was specified in PSDsoft

Unchanged

All other csiop registers

Cleared to 00h

Unchanged

VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at power-up and warm reset

conditions.

Table 203.

Function status during power-up reset, warm reset, power-down mode (continued)

Port configuration or

Power-up reset

Warm reset

APD Power-down mode

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UPSD3422EB40U6 Datasheet(PDF) 257 Page - STMicroelectronics

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