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UPSD3422EB40U6 Datasheet(PDF) 259 Page - STMicroelectronics |
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UPSD3422EB40U6 Datasheet(HTML) 259 Page - STMicroelectronics |
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259 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 PSD module 259/300 28.6.4 4-pin JTAG ISP (default) The four basic JTAG pins on Port C are enabled for JTAG operation at all times. These pins may not be used for other I/O functions. There is no action needed in PSDsoft Express to configure a device to use 4-pin JTAG, as this is the default condition. No 8032 firmware is needed to use 4-pin ISP because all ISP functions are controlled from the external JTAG program/test equipment. Figure 91 shows recommended connections on a circuit board to a JTAG program/test tool using 4-pin JTAG. It is required to connect the RST output signal from the JTAG program/test equipment to the RESET_IN input on the UPSD34xx. The RST signal is driven by the equipment with an Open Drain driver, allowing other sources (like a push button) to drive RESET_IN without conflict. Note: The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 91. Figure 91. Recommended 4-pin JTAG connections 1. For 5 V UPSD34xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5 V system VDD. 2. For 3.3 V UPSD34xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3 V system VCC. 3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESETIN. TMS - PC0 TCK - PC1 SRAM STBY or I/O - PC2 GENERAL I/O - PC3 GENERAL I/O - PC4 TDI - PC5 TDO - PC6 GENERAL I/O - PC7 JTAG CONN. 100k typical TMS TCK TDI TDO GENERAL I/O SIGNALS GND VCC (1,2) RST (3) uPSD34xx 0.01 µF CIRCUIT BOARD JTAG Programming or Test Equipment Connects Here 10k PUSH BUTTON or ANY OTHER RESET SOURCE DEBUG OPTIONAL TEST POINT 100k RESETIN AI10457 Obsolete Product(s) - Obsolete Product(s) |
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