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EM6620WS27 Datasheet(PDF) 50 Page - EM Microelectronic - MARIN SA |
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EM6620WS27 Datasheet(HTML) 50 Page - EM Microelectronic - MARIN SA |
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50 / 56 page ![]() R EM6620 Copyright © 2005, EM Microelectronic-Marin SA 50 www.emmicroelectronic.com Conditions: Vdd=3.0V, T=25°C, with internal voltage regulator (unless otherwise specified) Parameter Conditions Symb. Min. Typ. Max. Unit ACTIVE Supply Current (note2,3) IVDDa2 2.1 3.1 µA (in active mode with LCD on) -20 ... 85°C (note2,3) IVDDa2 3.5 µA STANDBY Supply Current IVDDh2 0.5 0.7 µA (in Halt mode, LCDOff) -20 ... 85°C IVDDh2 0.9 µA SLEEP Supply Current IVDDs2 0.15 0.28 µA -20 ... 85°C IVDDs2 0.3 µA POR static level -20 ... 85°C, No Load on Vreg VPOR2 0.95 1.25 V RAM data retention -20 ... 85°C Vrd2 1.2 V Regulated voltage Halt Mode, No Load Vreg 1.2 1.4 1.7 V Note 2: LCD Display NOT connected. Note 3: For test reasons, the user has to provide a test loop with successive writing and reading of two different addresses (5 instructions should be reserved for this measurement). 18.5 SVLD and Input Comparator Conditions: Standard operating conditions (unless otherwise specified) Parameter Conditions Symb. Min. Typ. Max. Unit SVLD voltage Level -10 ... 60 °C VSVLD 0.92 VSVLDNom VSVLDNOM 1.08 VSVLDNom V -20 ... 85 °C VSVLD 0.9 VSVLDNom VSVLDNOM 1.1 VSVLDNom V Input Comparator -10 ... 60 °C VSVLD 0.92 VSVLDNom VSVLDNOM 1.08 VSVLDNom V VINMax=VDD+0.2V VDD= VSVLDNom -20 ... 85 °C VSVLD 0.9 VSVLDNom VSVLDNOM 1.1 VSVLDNom V Input Comparator voltage dependency versus VDD -20 ... 85 °C dVSVLD/dVDD -100 mV/V Note 4: VSVLDNom is coming from the SVLD option Mask definition sheet (chapter 16.1.4). 18.6 Oscillator Conditions: T=25 °C (unless otherwise specified) Parameter Conditions Symb. Min. Typ. Max. Unit Temperature stability +15 ... +35 °C df/f x dT 0,3 ppm /°C Voltage stability (note 5) VDD=1,4 - 1,6 V df/f x dU 5 ppm /V Input capacitor Ref VSS Cin 5,6 7 8,4 pF Output capacitor Ref VSS Cout 12,1 14 15,9 pF Transconductance 50mVpp,VDDmin Gm 2.5 15.0 µA/V Oscillator start voltage Tstart < 10 s Ustart VDDmin V Oscillator start time VDD > VDDMin tdosc 0.5 3 s System start time (oscillator + cold start + reset) tdsys 1.5 4 s Oscillation detector frequency VDD > VDDmin tDetFreq 12 kHz Note 5 ; applicable only for the versions without the internal voltage regulator |
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