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EM6620WS27 Datasheet(PDF) 20 Page - EM Microelectronic - MARIN SA

Part # EM6620WS27
Description  Ultra Low Power Microcontroller with 4x8 LCD Driver
PDF  56 Pages
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Manufacturer  EMMICRO [EM Microelectronic - MARIN SA]
Direct Link  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6620WS27 Datasheet(HTML) 20 Page - EM Microelectronic - MARIN SA

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EM6620
Copyright
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6.6 Port B registers
Table 6.6.1 Register RegPBData
Bit
Name
Reset
R/W
Description
3
PBData[3]
-
R* /W
PB[3] input and output
2
PBData[2]
-
R* /W
PB[2] input and output
1
PBData[1]
-
R* /W
PB[1] input and output
0
PBData[0]
-
R* /W
PB[0] input and output
R* : Direct read on port B terminal (not the internal register read).
Table 6.6.2 Register RegPBCntl
Bit
Name
Reset
R/W
Description
3
PBIOCntl[3]
0
R/W
I/O control for PB[3]
2
PBIOCntl[2]
0
R/W
I/O control for PB[2]
1
PBIOCntl[1]
0
R/W
I/O control for PB[1]
0
PBIOCntl[0]
0
R/W
I/O control for PB[0]
Default "0" is: PortB in input mode
Table 6.6.3 Register RegPB0Comp
Bit
Name
Reset
R/W
Description
3
--
--
--
2
PB0CompResult
0
R
Comparator result flag
1
PB0CompEnable
0
R/W
Comparator measurements enable
0
PB0CompSelect
0
R/W
Dynamic input Comparator function
Default "0" is: Power supply voltage level detection
Table 6.6.4 register OPTFSelPB
Bit
Name
power on
value
R/W
Description
3
PB1HzOut
0
R/W
Ck[1] output on PB[2]
2
PB2kHzOut
0
R/W
Ck[12] output on PB[1]
1
PB32kHzOut
0
R/W
Ck[16] output on PB[0]
0
NoInputRes
0
R/W
No Input Reset From Port A
Default "0" is: No frequency output, Port A can reset the EM6620.
Table 6.6.5 option register OPTNoPdPB
Bit
Name
power on
value
R/W
Description
3
NoPdPB[3]
0
R/W
No pull-down on PB[3]
2
NoPdPB[2]
0
R/W
No pull-down on PB[2]
1
NoPdPB[1]
0
R/W
No pull-down on PB[1]
0
NoPdPB[0]
0
R/W
No pull-down on PB[0]
Default "0" is: Pull-down on
Table 6.6.6 option register OPTNchOpDPB
Bit
Name
power on
value
R/W
Description
3
NchOpDPB[3]
0
R/W
Nch. Open Drain on PB[3]
2
NchOpDPB[2]
0
R/W
Nch. Open Drain on PB[2]
1
NchOpDPB[1]
0
R/W
Nch. Open Drain on PB[1]
0
NchOpDPB[0]
0
R/W
Nch. Open Drain on PB[0]
Default "0" is: CMOS on PB[3..0]



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