EM6620WS27 datasheet(31/56 Pages) EMMICRO

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EM6620

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9. Interrupt Controller

The EM6620 has 12 different interrupt request sources individually maskable. These are:

External(5)

- Port A,

PA[3] .. PA[0] inputs

- Compare

PB[0] input

Internal(8)

- Prescaler

ck[1], Blink, 32Hz/8Hz

- Millisecond Counter

1/10Sec or 1Sec

- 10-bit Counter

Count0, CountComp

- SVLD

End of measure

The SVLD and the Compare share the same interrupt line.

To be able to send an interrupt to the CPU, at least one of the interrupt request flags must be set (IRQxx) and

the general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt

request flags can only be set by a positive edge of IRQxx with the corresponding mask register bit

(MaskIRQxx) set to 1.

At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any

interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.

After each read operation on the interrupt request registers RegIRQ1, RegIRQ2 or RegIRQ3 the contents of

the addressed register are reset. Therefore one has to make a copy of the interrupt request register if there

was more than one interrupt to treat. Each interrupt request flag may also be reset individually by writing 1 into

it (ClrIntBit).

Interrupt handling priority must be resolved through software by deciding which register and which flag inside

the register need to be serviced first.

Since the CPU has only one interrupt subroutine and because the IRQxx registers are cleared after reading,

the CPU does not miss any interrupt request which comes during the interrupt service routine. If any occurs

during this time a new interrupt will be generated as soon as the software comes out of the current interrupt

subroutine.

Figure 22. Interrupt Controller Block Diagram

Interrupt Request

Capture Register

12 Input-OR

Read

ClrIntBit

Reset

General

INT En

IRQ to µP

One of these Blocks for each IRQ

DB[n]

IRQxx

Write

Mask

Write

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