| Electronic Components Datasheet Search |
|
MCP2518FD Datasheet(PDF) 44 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MCP2518FD Datasheet(HTML) 44 Page - Microchip Technology |
|
44 / 96 page ![]() MCP2518FD DS20006027A-page 44 2019 Microchip Technology Inc. REGISTER 3-22: CiBDIAG1 – BUS DIAGNOSTICS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 DLCMM ESI DCRCERR DSTUFERR DFORMERR — DBIT1ERR DBIT0ERR bit 31 bit 24 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXBOERR — NCRCERR NSTUFERR NFORMERR NACKERR NBIT1ERR NBIT0ERR bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EFMSGCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EFMSGCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 DLCMM: DLC Mismatch bit During a transmission or reception, the specified DLC is larger than the PLSIZE of the FIFO element. bit 30 ESI: ESI flag of a received CAN FD message was set. bit 29 DCRCERR: Same as for nominal bit rate (see below). bit 28 DSTUFERR: Same as for nominal bit rate (see below). bit 27 DFORMERR: Same as for nominal bit rate (see below). bit 26 Unimplemented: Read as ‘0’ bit 25 DBIT1ERR: Same as for nominal bit rate (see below). bit 24 DBIT0ERR: Same as for nominal bit rate (see below). bit 23 TXBOERR: Device went to bus-off (and auto-recovered). bit 22 Unimplemented: Read as ‘0’ bit 21 NCRCERR: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. bit 20 NSTUFERR: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. bit 19 NFORMERR: A fixed format part of a received frame has the wrong format. bit 18 NACKERR: Transmitted message was not acknowledged. bit 17 NBIT1ERR: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. bit 16 NBIT0ERR: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. bit 15-0 EFMSGCNT<15:0>: Error Free Message Counter bits |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |