HC705RC16GRSSLASHD datasheet(57/120 Pages) NXP

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Parallel Input/Output (I/O)

Input/Output Programming

MC68HC705RC16 — Rev. 3.0

General Release Specification

Parallel Input/Output (I/O)

the ports to inputs. Writing a one to a DDR bit sets the corresponding

port bit to output mode. Port C pins PC4–PC7 are available only with the

44-lead PLCC package.

NOTE:

Only four bits of port C are bonded out in 28-pin packages for the

MC68HC705RC16, although port C is truly an 8-bit port. Since pins

PC4–PC7 are unbonded, software should include the code to set their

respective data direction register locations to outputs to avoid floating

inputs.

7.6 Input/Output Programming

Port pins may be programmed as inputs or outputs under software

control. The direction of the pins is determined by the state of the

corresponding bit in the port data direction register (DDR). Each I/O port

has an associated DDR. Any I/O port pin is configured as an output if its

corresponding DDR bit is set to a logic 1. A pin is configured as an input

if its corresponding DDR bit is cleared to a logic 0.

At power-on or reset, all DDRs are cleared, which configures all pins as

inputs. The data direction registers are capable of being written to or

read by the processor. During the programmed output state, a read of

the data register actually reads the value of the output data latch and not

the I/O pin.

Table 7-1. I/O Pin Functions

Access

DDR

I/O Pin Functions

Write

The I/O pin is in input mode. Data is written into the output

data latch.

Write

Data is written into the output data latch and output to the

I/O pin.

Read

The state of the I/O pin is read.

Read

The I/O pin is in an output mode. The output data latch is read.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC16GRS/D Datasheet(PDF) 57 Page - NXP Semiconductors

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