DA9068 datasheet(57/185 Pages) RENESAS

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DA9068

System PMIC for Multi-Core Application Processors

Datasheet

Revision 3.5

21-Feb-2022

CFR0011-120-00

57 of 184

4*C

1*C

VBAT_S

TEMP1

TEMP2

5 TO 1

MUX

12 BIT

ADC

D[11:0]

ADC_REF

ADC_GND

3 TO 8

ENCODER

ADC_CLK

EOC

SEL[2:0]

DIGITAL CONTROL

SIGNALS

SH PRE -AMPLIFIER

ADC_TOP

2.5V

5*C

3*C

2.5V

ADCIN1

NTC

ADCIN_SEL[1:0]

ADCIN2

ADCIN3

ADCIN4

4 TO 1

MUX

Figure 7: GPADC Block Diagram

On DA9068, the A-to-D conversion is performed by a switched capacitor (SC) successive

approximation register (SAR) ADC. The actual ADC is preceded by a 5:1 input multiplexer that

controls the channel selection, routes the appropriate input signal to the SC circuit, and ensures the

inter-channel isolation. The input voltage range of the SC ADC core is from 0 V to 2.5 V, hence any

input signal outside this range has to be pre-scaled before being routed to the input of the converter.

The ADC core is supplied from the internal 2.5 V VCORE rail, which is also used to provide the

positive reference voltage for the ADC. A dedicated quiet VSS signal is used for the negative

reference voltage of SC circuit.

The implemented track-and-hold circuit ensures a stable voltage on the input of the SC ADC during

the conversion. Figure 8 shows the polarity and the timing of the external and internal signals

controlling the track and hold sequence of the converter. The clock (fCLK = 0.5 MHz) and the enable

signal (EN) are provided by the main PM control logic, while all the other signals are internally

generated. The timing diagram illustrates a tracking period of 13 clock cycles, that is 26 µs (inclusive

of 10 µs auto-zero time) and a conversion period of 24 µs, hence a total ADC conversion cycle of

50 µs.

The end of the conversion is flagged by the EOC signal which indicates the availability of the data

bits D[11:0]. Once the PM controller has read the result, it de-asserts the EN signal which terminates

the current conversion cycle. A new cycle can be started on the following rising edge of the clock.

The channel selection control signals SEL[2:0] must be present prior to, or at least coincident with,

the assertion of the ADC enable signal. This is to ensure that the tracking period is not affected by

late assertion of the external digital controls. For the same reason, in case of dynamic control of the

TEMP and VF current sources they have to be enabled (turned on) at least 100 µs before the next

NTC or respectively VF measurement.

DA9068 Datasheet(PDF) 57 Page - Renesas Technology Corp

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