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May 10, 2016

IDT 89HPES10T4G2 Data Sheet

Pin Characteristics

Note: Some input pads of the PES10T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate

levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left

floating can cause a slight increase in power consumption.

Function

Pin Name

Type

Buffer

I/O

Type

Internal

Resistor1

Notes

PCI Express Inter-

face

PE0RN[3:0]

I

PCIe

differential2

Serial Link

PE0RP[3:0]

I

PE0TN[3:0]

O

PE0TP[3:0]

O

PE2RN[1:0]

I

PE2RP[1:0]

I

PE2TN[1:0]

O

PE2TP[1:0]

O

PE4RN[1:0]

I

PE4RP[1:0]

I

PE4TN[1:0]

O

PE4TP[1:0]

O

PE6RN[1:0]

I

PE6RP[1:0]

I

PE6TN[1:0]

O

PE6TP[1:0]

O

PEREFCLKN[0]

I

HCSL

Diff. Clock

Input

Refer to Table 9

PEREFCLKP[0]

I

REFCLKM

I

LVTTL

Input

pull-down

SMBus

MSMBADDR[4:1]

I

LVTTL

Input

pull-up

MSMBCLK

I/O

STI3

pull-up on board

MSMBDAT

I/O

STI

pull-up on board

SSMBADDR[5,3:1]

I

Input

pull-up

SSMBCLK

I/O

STI

pull-up on board

SSMBDAT

I/O

STI

pull-up on board

General Purpose I/O

GPIO[11,7:0]

I/O

LVTTL

STI,

High Drive

pull-up

System Pins

CCLKDS

I

LVTTL

Input

pull-up

CCLKUS

I

Input

pull-up

MSMBSMODE

I

Input

pull-down

PERSTN

I

STI

RSTHALT

I

Input

pull-down

SWMODE[2:0]

I

Input

pull-down

Table 8 Pin Characteristics (Part 1 of 2)