5

Typical application diagram

Figure 3. Typical application diagram for Vout > 1.25 V

Vi

INHIBIT

Isc

FILT C

GND

STAB

OCM

ADJ

Vo

RHFL6000L

OFF

ON

VIN

VOUT

IN+

R2

R1

Cin

Cfilt

Cout

Cbyp

Rsc

Rload

For VO > 1.25 V, the divider resistor pair R2 and R1 are tied between VO, ADJ/SENSE (middle point), and GND

pins respectively; FILT_C and IN+ pins are externally shorted (see Figure 3. Typical application diagram for Vout >

1.25 V). In this case, the arrangement of the feedback control loop is identical to the one used for generating VO >

1.25 V in the RHFL6000A device.

Figure 4. Typical application diagram for Vout = 1.25 V

Vi

INHIBIT

Isc

FILT C

GND

STAB

OCM

ADJ

Vo

RHFL6000L

OFF

ON

VIN

VOUT

IN+

Cin

Cfilt

Cout

Rsc

Rload

For VO = 1.25 V, FILT_C must be shorted to IN+ and VO to ADJ/SENSE terminals (see Figure 4. Typical

application diagram for Vout = 1.25 V). Also in this case, the arrangement of the feedback control loop is identical

to the one used for generating VO = 1.25 V in the RHFL6000A device.

RHFL6000L

Typical application diagram

DS14125 - Rev 1

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