9

Application information

With reference to Figure 3a, to adjust the output voltage values VO > 1.25 V, the R2 resistor must be connected

between the VO and ADJ/SENSE pins. The R1 resistor must be connected between ADJ/SENSE and ground.

FILT_C and IN+ pins must be externally shorted together.

9.1

Reliability considerations

A reverse operation (supply voltage applied on Vo instead of Vi) could expose the device to degradation in its

regulation performances (line, load) when VO - VI ≥ 2 V.

The STAB pin is for tuning the control loop stability by a proper RC impedance put between this node and

GND. Powering this node with a low impedance source, for VI > 3.75 V the device could undergo regulation

performance degradation.

9.2

Notes on the 16-pin hermetic flat package

The RHFL6000L adjustable voltage regulator is available in a high thermal dissipation 16-pin hermetic FLAT

package, whose bottom flange is metallized to allow direct soldering or gluing to a heatsink (efficient thermal

conductivity). The upper metallic package lid is connected to ground. The bottom metallization is electrically

floating.

9.3

FPGA supply

FPGA devices are very sensitive to VDD transients beyond a few % of their nominal supply voltage (usually 1.5

V).

The RHFL6000L includes specific integrated circuitry designed to absorb the output transients under heavy-ion

beams, rendering it suitable for safe FPGA supply operation.

RHFL6000L

Application information

DS14125 - Rev 1

page 16/28