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ICS84329BYLF Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # ICS84329BYLF
Description  700MHZ, Low Jitter, Crystal-to-3.3V LVPECL Frequency Synthesizer
PDF  19 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS84329BYLF Datasheet(HTML) 3 Page - Renesas Technology Corp

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84329B DATA SHEET
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
3
REVISION B 07/29/14
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Name
Type
Description
M0, M1, M2,
M3, M4, M5,
M6, M7, M8
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
N0, N1
Input
Pullup
Determines N output divider value as defined in Table 3C, Function Table. LVCMOS/LVTTL
interface levels.
VEE
Power
Negative supply pins.
TEST
Output
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
VCC
Power
Core supply pins.
FOUT,
nFOUT
Output
Differential output pair for the synthesizer. LVPECL interface levels.
OE
Input
Pullup
Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the
outputs are disabled and drive differential low: FOUT = LOW, nFOUT = HIGH. LVCMOS /
LVTTL interface levels.
nc
Unused
No connect.
S_CLOCK
Input
Pulldown
Clocks the serial data present at S_DATA input into the shift register on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL
interface levels.
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the M divider.
LVCMOS/LVTTL interface levels.
VCCA
Power
Analog supply pin.
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
nP_LOAD
Input
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and
when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL interface
levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k



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