R7F0C902B2 datasheet(64/90 Pages) RENESAS

64 / 90 page

R7F0C901B2, R7F0C902B2

25. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

C)

Page 64 of 87

R01DS0236EJ0100 Rev.1.00

Jun 24, 2014

(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,

corresponding CSI00 only) (2/2)

(TA =

40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Parameter

Symbol

Conditions

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Unit

4.0 V

 VDD  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k



110

SIp setup time

(to SCKp

) Note 2

tSIK1

2.7 V

 VDD < 4.0 V,

2.3 V

 Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k



110

4.0 V

 VDD  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k



SIp hold time

(from SCKp

) Note 2

tKSI1

2.7 V

 VDD < 4.0 V,

2.3 V

 Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k



4.0 V

 VDD  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k



Delay time from SCKp



SOp output

Note 2

tKSO1

2.7 V

 VDD < 4.0 V,

2.3 V

 Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k



Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode

for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode

Remarks 1. Rb[

]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)

load capacitance, Vb[V]: Communication line voltage

2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),

g: PIM and POM number (g = 1)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00))

4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.

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