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S12SCIV3/D Datasheet(PDF) 9 Page - NXP Semiconductors

Part # S12SCIV3/D
Description  The SoC Guide provides information about the MC9S12KG128 device made up of standard HCS12 blocks and the HCS12 processor core
PDF  98 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

S12SCIV3/D Datasheet(HTML) 9 Page - NXP Semiconductors

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SoC Guide — MC9S12KG128 V01.01
Figure 1-1
MC9S12KG128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 1-2
MC9S12KG128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2-1
Pin assignments 112 LQFP for MC9S12KG128 . . . . . . . . . . . . . . . . . . . . . . 25
Figure 2-2
Pin assignments in 80 QFP for MC9S12KG128 . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-3
PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2-4
Loop Controlled Pierce Oscillator Connections (XCLKS=1) . . . . . . . . . . . . . 31
Figure 2-5
Full Swing Pierce Oscillator Connections (XCLKS=0). . . . . . . . . . . . . . . . . . 31
Figure 2-6
External Clock Connections (XCLKS=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3-1
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 19-1 Recommended PCB Layout for 112LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 19-2 Recommended PCB Layout for 80QFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure A-1
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure A-2
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure A-3
Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure A-4
SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure A-5
SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure A-6
SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure A-7
SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure A-8
General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure B-1
80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . 94
Figure B-2
112-pin LQFP Mechanical Dimensions (case no. 987) . . . . . . . . . . . . . . . . 95
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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