SPMC68CK338CPV14 datasheet(26/133 Pages) NXP

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MOTOROLA

MC68CK338

MC68CK338TS/D

PTP — Periodic Timer Prescaler Control

0 = Periodic timer clock not prescaled

1 = Periodic timer clock prescaled by 512

The reset state of PTP is the complement of the state of the MODCLK signal at the rising edge of

RESET.

PITM[7:0] — Periodic Interrupt Timer Modulus

This is an 8-bit timing modulus. The period of the timer can be calculated as follows:

where

PIT Period = Periodic interrupt timer period

PITM[7:0] = Periodic interrupt timer register modulus

fref = Synthesizer reference of external clock input frequency

Prescaler = 1 if PTP = 0 or 512 if PTP = 1

3.5 External Bus Interface

The external bus interface (EBI) transfers information between the internal MCU bus and external de-

vices. The external bus has 24 address lines and 16 data lines.

The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and

long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the size

(SIZ1 and SIZ0) and data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles may be

required for dynamically sized transfer.

Port width is the maximum number of bits accepted or provided during a bus transfer. External devices

must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,

the address space, the size of the transfer, and the type of cycle. The selected device controls the length

of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity

of an address and provide timing information for data. The EBI operates in an asynchronous mode for

any port width.

To add flexibility and minimize the necessity for external logic, MCU chip-select logic can be synchro-

nized with EBI transfers. Chip-select logic can also provide internally-generated bus control signals for

these accesses. Refer to 3.6 Chip-Selects for more information.

3.5.1 Bus Control Signals

The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the

beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals

(FC[2:0]). The size signals indicate the number of bytes remaining to be transferred during an operand

cycle. They are valid while the address strobe AS is asserted.

Table 13 shows SIZ0 and SIZ1 encoding. The read/write (R/W) signal determines the direction of the

transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle,

and is valid while AS is asserted. The R/W signal only changes state when a write cycle is preceded by

a read cycle or vice versa. The signal can remain low for two consecutive write cycles.

PIT Period

4 PITM[7:0]

() Prescaler

()

ref

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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