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ISL81802EVAL1Z Datasheet(PDF) 38 Page - Renesas Technology Corp |
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ISL81802EVAL1Z Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 45 page ![]() ISL81802 6. Layout Guidelines R16DS0033EU0101 Rev.1.01 Page 38 of 44 Oct.15.20 6.2 General EPAD Design Considerations Figure 45 shows how to use vias to remove heat from the IC. Fill the thermal pad area with vias. A typical via array fills the thermal pad footprint so that their centers are three times the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder wicking through during reflow. Connect all vias to the ground plane. The vias must have a low thermal resistance for efficient heat transfer. Ensure a complete connection of the plated through hole to each plane. Figure 45. PCB Via Pattern |
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