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ICS1524AMLF Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # ICS1524AMLF
Description  Dual Output Phase Controlled SSTL_3/PECL Clock Generator
PDF  25 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1524AMLF Datasheet(HTML) 6 Page - Renesas Technology Corp

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ICS1524A
6
Detailed Register Description
Name:
Input Control
Register:
0 h
Index:
Read / Write
Bit
Name
Description
0
PDen
Charge Pump Enable
0 = External Enable via PDEN pin
1 = Always Enable
1
PD_Pol
Charge Pump Enable Polarity
0 = Active High
1 = Active Low
2
Ref_Pol
External Reference Polarity —
Edge of input signal on which Phase/Frequency Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3
Fbk_Pol
External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
4
Fbk_Sel
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
5
Func_Sel
Function Output Select — Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6
EnPLS
Enable LOCK/REF (pin14) Output
7
EnDLS
Bit Name Bit #
Reset Value
Description
PDen
0
1
Charge Pump Enable
PD_Pol
1
0
Charge Pump Enable Polarity
Ref_Pol
2
0
External Reference Polarity
Fbk_Pol
3
0
External Reference Feedback Polarity
Fbk_Sel
4
0
External Feedback Select
Func_Sel
5
0
Function Output Select
EnPLS
6
1
Enable PLL Lock Status Output on LOCK/REF pin
EnDLS
7
0
Enable DPA Lock Status Output on LOCK/REF pin
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